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TDA7437N
Digitally controlled audio processor
Features
Input multiplexer - Four stereo, one mono input, and one differential input - Selectable input gain for optimal adaptation to different sources Fully programmable loudness function Volume control in 1dB steps including gain up to 16dB Zero crossing mute, soft mute and direct mute Bass and treble control Four speaker attenuators- four independent speakers control in 1dB steps for balance and fader facilities Pause detector programmable threshold All functions programmable via serial I2C bus low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways either via the serial bus (Mute byte, bit D0), or directly on pin 28 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology. LQFP44

Description
The audioprocessor TDA7437N is an upgrade of the TDA731X audioprocessor family. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very
Order codes
Part numbers E-TDA7437N E-TDA7437NTR Package LQFP44 (10x 10x 1.4mm) LQFP44 (10x 10x 1.4mm) Packing Tray Tape and reel
December 2006
Rev 2
1/34
www.st.com 1
TDA7437N
Contents
1 2 3 PIN descriptions and electrical specifications . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmission without acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 4.4 4.5 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Mute and pause features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Direct mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Speakers mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Zero crossing mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pause function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 No symmetrical bass cut response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transmitted data (send mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TDA7437N I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Loudness stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IN-OUT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Bass & mid filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/34
TDA7437N
5.14
Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 7 8
Curves of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
TDA7437N
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input stage gain middle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/34
TDA7437N
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CLD and CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing diagram of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge on the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power on time constant vs CREF capacitor CREF = 4.7mF . . . . . . . . . . . . . . . . . . . . . . . 28 Power on time constant vs CREF capacitor CREF = 10mF . . . . . . . . . . . . . . . . . . . . . . . . 28 Power on time constant vs CREF capacitor CREF = 22mF . . . . . . . . . . . . . . . . . . . . . . . . 28 SVRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft mute ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Soft mute OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Zero crossing mute ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Zero crossing mute OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pause detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Symmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 unsymmetrical bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test board diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LQFP44 (10x10) Mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . 32
5/34
PIN descriptions and electrical specifications
TDA7437N
1
PIN descriptions and electrical specifications
Figure 1. Pin description
OUT_LF 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 STEREO4_L STEREO1_L STEREO2_L STEREO3_L LOUD_L CSM IN_L MUXOUT_L DIFF_L DIFFGND_L MID_RI TREB-L PAUSE
CREF
44 43 42 41 40 39 38 37 36 35 34 TREB_R IN_R MUXOUT_R LOUD_R DIFFGND_R DIFF_R STEREO4_R STEREO1_R STEREO2_R STEREO3_R MONO 1 2 3 4 5 6 7 8 9 10 11 OUT_RF OUT_LR MID_LI MID_LO OUT_RR SMEXT BASS_RO BASS_RI BASS_LO BASS_LI MID_RO
DGND
AGND
DVDD
ADDR
AVDD
SDA
SCL
D96AU435B
Table 1.
Symbol
Absolute maximum ratings
Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
AVDD, DVDD Operating supply voltage Tamb Tstg Operating ambient temperature Storage temperature range
Table 2.
Symbol Rth j-amb
Thermal data
Parameter Thermal resistance junction to pins Max. Value 150 Unit C/W
Table 3.
Symbol AVDD, DVDD VCL THD S/N SC
Quick reference data
Parameter Supply voltage (AVDD and DVDD must be at the same potential) Max. input signal handling Total harmonic distortion V = 1Vrms f = 1KHz Signal to noise ratio Channel separation f = 1KHz Min. 6 2.1 Typ. 9 2.6 0.01 111 95 0.8 Max. 10.2 Unit V Vrms % dB dB
6/34
TDA7437N Table 3.
Symbol Input gain 1dB step Volume control 1dB step Treble control 2dB step Bass control 2dB step Middle control 2dB step
PIN descriptions and electrical specifications Quick reference data (continued)
Parameter Min. 0 -63 -14 -14 -14 -79 0 100 Typ. Max. 15 16 +14 +14 +14 0 20 Unit dB dB dB dB dB dB dB dB
Fader and balance control 1dB step Loudness control 1dB step Mute attenuation
7/34
IN_L
MUXOUT_L 21 20 12 44 30 31 25 24
LOUD_L
TREBL_L
MULTIPLEXER
IN_R
MUXOUT_R
22nF 2.7K
18nF 100nF 5.6K
BASS_RO)
2.2F
TREB_R
100nF
SMEXT
47nF
PAUSE
8/34
2.2F 47nF 5.6nF 2.7K 22nF 100nF 5.6K 18nF 100nF MID_LO MID_LI BASS_LO BASS_LI
Figure 2.
4 x 470nF
STEREO1_L
16
Block diagram
STEREO2_L SPKR ATT
17 34 OUT_LF
STEREO3_L
18
STEREO4_L INGAIN MIDDLE S-MUTE VOLUME + LOUDN TREBLE BASS
15
2 x 4.7F
DIFF_L
14
SPKR ATT
33
OUT_LR
DIFFGND_L
13
40 38 I2C BUS DECODER + LATCHES 37 36
ADDR SCL SDA DIGGND
PIN descriptions and electrical specifications
5 x 470nF
MONO
11
STEREO1_R
8
STEREO2_R
9
STEREO3_R INGAIN TREBLE MIDDLE VOLUME + LOUDN
10 BASS S-MUTE SPKR ATT 29 OUT_RR
STEREO4_R
7
2 x 4.7F
DIFF_R
6
DIFFGND_R
5 MUTE CONTROL SOFT, ZERO SUPPLY 39 CREF 22F 47nF LOUD_R 3 2 4 1 23 MID_RO 5.6nF 22 MID_RI 27 BASS_RI 26 28 35 19 CSM
D95AU249B
DVDD
41
SPKR ATT
32
OUT_RF
AVDD
42
43
AGND
47nF
TDA7437N
TDA7437N
Electrical characteristics
2
Electrical characteristics
(AVDD, DVDD = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Table 4.
Symbol
Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
Input selector (mono and stereo inputs) RI VCL SI RL GI MIN GI MAX Gstep Ea VDC Input resistance Clipping level Input separation Output load resistance Minimum input gain Maximum input gain Step resolution Set error Adjacent gain steps DC steps GIMIN to GIMAX 3 mV pin 7 to 11 and 15 to 18 d 0.3% 70 2.1 80 2 -0.75 14 0.5 -1.0 0 15 1.0 0 0.5 +0.75 16 1.5 1.0 10 100 2.6 95 130 K VRMS dB K dB dB dB dB mV
Differential input (Pin 5, 6, 13, 14) Input selector BIT D4 = 0 (0dB) RI Input resistance Input selector BIT D4 = 1(6dB) Common mode rejection ratio Distortion Input noise VCM = 1VRMS ; f = 1KHz VI = 1VRMS 20Hz to 20KHz; Flat; D6 = 0 D4 = 0 GDIFF Differential gain D4 = 1 -7 -6 -5 dB -1 14 45 20 70 0.01 5 0 1 0.08 26 K dB % V dB 10 15 20 K
CMRR d eIN
Volume control RI GMAX AMAX Input resistance Maximum gain Maximum attenuation Pin 2 and 20 31 15 61 0.5 G = 16 to -20dB EA Et Attenuation set error G = -20 to -63dB Tracking error -2.75 2.75 2 dB dB -1.0 44 16 63.75 1.0 0 57 17 66.5 1.5 1.0 K dB dB dB dB
ASTEPC Step resolution coarse atten.
9/34
Electrical characteristics Table 4.
Symbol
TDA7437N
Electrical characteristics (continued)
Parameter Test condition Adjacent gain steps Min. -5 -3 0.5 Typ. Max. +5 +3 5 Unit mV mV mV
VDC
DC steps
Adjacent attenuation steps From 0dB to AMAX
Loudness control (Pin 4, 12) RI AMAX Astep Internal resistor Maximum attenuation Step resolution Loud = On 35 19 0.5 50 20 1 65 21 1.5 K dB dB
Zero crossing mute WIN = 11 VTH Zero crossing threshold (1) WIN = 10 WIN = 01 WIN = 00 AMUTE VDC Mute attenuation DC step 0dB to Mute 80 35 70 140 280 100 0.1 3 mV mV mV mV dB mV
Soft mute AMUTE Mute attenuation CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN OFF current Pullup resistor (pin 28) (pin 28) Level high (pin 28) Level low Soft mute active VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN
(2)
50 0.8 25 20
65 1.5 45 40 2 100 2.0 60 60
dB ms ms mA A K V 1 V
TDON
ON delay time
TDOFF RINT VSMH VSML
3.5
Bass control Crange Astep Rg Control range Step resolution Internal feedback resistance 11.5 1 31 14 2 44 16 3 57 dB dB K
Middle control Crange Astep Rg Control range Step resolution Internal feedback resistance 11.5 1 17.5 14 2 25 16 3 32.5 dB dB K
10/34
TDA7437N Table 4.
Symbol Treble control CRANGE Control range Astep Step resolution
Electrical characteristics Electrical characteristics (continued)
Parameter Test condition Min. Typ. Max. Unit
13 1
14 2
15 3
dB dB
Speaker attenuators CRANGE Control range Astep AMUTE EA VDC Step resolution Output mute attenuation Attenuation set error DC steps AV = 0 to -40dB Data word = 1111XXXX AV = 0 to -40dB Adjacent attenuation steps 0.1 0.5 80 79 1 100 1.5 3 1.5 dB dB dB dB mV
Audio output Vclip RL RO VDC Clipping level Output load resistance Output impedance DC voltage level d = 0.3% 2.1 2 50 3.5 90 3.8 140 4.1 2.6 Vrms K W V
Pause detector WIN = 11 WIN = 10 VTH Pause threshold WIN = 01 WIN = 00 IDELAY VTHP General VCC ICC PSRR Supply voltage Supply current Power supply rejection ratio Output noise eNO f = 1KHz Output muted (B = 20 to 20kHz flat) All gains 0dB (B = 200 to 20kHz flat) Total tracking error AV = 0 to -20dB AV = -20 to -60dB S/N SC Signal to noise ratio Channel separation L - R All Gains = 0dB; VO = 2.1Vrms 80 6 7 70 9 10 90 4 6 0 0 111 95 15 1 2 10.2 13 V mA dB V V dB dB dB dB Pull-up current Pause threshold 15 140 280 25 3.0 35 mV mV A V 35 70 mV mV
Et
11/34
Electrical characteristics Table 4.
Symbol d
TDA7437N
Electrical characteristics (continued)
Parameter Distortion Test condition VIN =1V all gain = 0dB Min. Typ.
0.01
Max.
0.08
Unit
%
Bus inputs VIL VlN IlN VO Input low voltage Input high voltage Input current Output voltage SDA acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.1 5 0.4 1 V V A V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold 2. Internal pullup resistor to Vs/2; "LOW" = softmute active
Note:
The ANGND and DIGGND layout wires must be kept separated. A 50 resistor is recommended to be put as far as possible from the device. The CLD - and CDR - can be short-circuited in applications providing 3 wires CD signal Figure 3. CLD and CDR
L+ L- =RR+ L+
CD
LRR+
TDA7437N
D02AU1384
CLD - = DIFFINLGND CDR - = DIFFINRGND
12/34
TDA7437N
I2C bus interface
3
I2C bus interface
Data transmission from the microprocessor to the TDA7437N, and vice versa, takes place through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pullup resistors to positive supply voltage must be externally connected).
3.1
Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2
Start and stop conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 6). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledgment after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
3.5
Transmission without acknowledgment
To avoid detection of the acknowledge clock pulse of the audioprocessor, the microprocessor can use a simpler transmission: it simply waits one clock pulse, and sends the new data. This is less protected from any errors and will decrease the immunity to noise.
13/34
I2C bus interface Figure 4. Data validity
SDA
TDA7437N
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 5.
Timing diagram of I2C Bus
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 6.
Acknowledge on the I2C Bus
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
14/34
TDA7437N
Software specification
4
4.1
Software specification
Interface protocol
The interface protocol comprises of:

A start condition (s) A chip address byte, (the LSB bit determines read (=1)/write (=0) transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S1 0 0 0 1 0 A LSB R/W ACK MSB XXX
SUBADDRESS LSB I A3 A2 A1 A0 ACK MSB
DATA 1 to DATA n LSB DATA ACK P
ACK = Acknowledge; S = Start; P = Stop; I = Auto increment; X = Not used Max clock speed 500kbits/s ADDRpin open A = 0 ADDRpin close to Vs A = 1
4.2
Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
4.3
Subaddress (receive mode)
Table 5.
MSB X X X I A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0
Subaddress (receive mode)
LSB A0 0 1 0 1 0 1 0 1 0 1 Input selector Loudness Volume Bass, Treble Speaker attenuator LF Speaker attenuator LR Speaker attenuator RF Speaker Attenuator RR Input gain middle Mute FUNCTION
15/34
Software specification
TDA7437N
4.4
Transmitted data
Table 6.
MSB X X X X X SM ZM
Send mode
LSB P
P = Pause (Active low) ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used
The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress.
4.5
Data byte specification
Table 7.
MSB D7 D6 D5 D4 D3 1 1 1 1 1 1 X X X 0 0 1 1 X 0 1 0 1 0 D2 0 0 0 0 1 1 X D1 0 0 1 1 0 0 X
Data byte specification
LSB Function D0 0 1 0 1 0 1 X Differential Stereo 1 Stereo 2 Stereo 3 Stereo 4 Mono DC connect (1) Half-diff 0dB (2) Half-diff -6dB (2) Full-diff 0dB (3) Full-diff -6dB (3)
1. Selected when using a 3 wire differential source (pins 5 and 13 shorted) 2. Selected when using a 4 wire differential source 3. OUTR-INR (OUTL-INR) short circuited internally (no need for external connection
Table 8.
MSB D7
Loudness
LSB D6 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 Function Loudness step 0dB 1dB 2dB 3dB
16/34
TDA7437N Table 8.
MSB D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 D3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 D2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
Software specification Loudness (continued)
LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Loudness step 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB 16dB 17dB 18dB 19dB 20dB Loudness off
Fine volume 0 0 1 1 0 1 0 1 0dB -0.25dB -0.5dB -0.75dB
Table 9.
MSB D7
Mute
LSB Function D6 D5 D4 D3 0 0 0 0 0 1 1 1 0 1 D2 D1 D0 1 1 1 Soft mute on soft mute with fast slope Soft mute with slow slope Zero mute Direct mute Reset
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Software specification Table 9.
MSB D7 D6 0 0 1 1 0 1 D5 0 1 0 1 D4 0 0 0 0 D3 D2 D1
TDA7437N Mute (continued)
LSB Function D0 Zero cross window (280mV) Zero cross window (140mV) Zerocross window (70mV) Zerocross window (35mV) Non symmetrical bass Symmetrical bass
Table 10.
MSB D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Volume
LSB Function D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
0 0 0 0 0 0 0 0 1 1 X
0 0 0 0 1 1 1 1 0 0 X
0 0 1 1 0 0 1 1 0 0 X
0 1 0 1 0 1 0 1 0 1 X X X X
16dB 8dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB Mute
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TDA7437N Table 11.
MSB D7 D6 D5 D4 D3 D2 D1
Software specification Speaker
LSB Function D0 1.25dB step 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1 0 0 1
0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 1 X X X
0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB Mute
Table 12.
MSB D7
Bass treble
LSB Function D6 D5 D4 D3 D2 D1 D0 Treble step 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB
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Software specification Table 12.
MSB D7 D6 D5 D4 D3 1 1 1 1 1 1 1 1 D2 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 0 0
TDA7437N Bass treble (continued)
LSB Function D0 1 0 1 0 1 0 1 0 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB Bass steps
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
-14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 126B 14dB
1
1 1
1
0 0
1 1
0 0
Table 13.
MSB D7
Input stage gain middle
LSB Function D6 D5 D4 D3 D2 D1 D0 In-gain step 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0dB 1dB 2dB 3dB
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TDA7437N Table 13.
MSB D7 D6 D5 D4 D3 0 0 0 0 1 1 1 1 1 1 1 1 D2 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1
Software specification Input stage gain middle (continued)
LSB Function D0 0 1 0 1 0 1 0 1 0 1 0 1 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB Middle step 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 126B 14dB
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Mute and pause features
TDA7437N
5
Mute and pause features
The TDA7437N provides three types of mute, controlled via I2C bus (see Table 9 Mute byte register).
5.1
Soft mute
Bit D0 = 1 Soft mute ON Bit D0 = 0 Soft mute OFF It allows an automatic soft muting and unmuting of the signal. The time constant is fixed by an external capacitor Csm inserted between pin Csm and ground. Once the external capacitor is fixed, two different slopes (time constant) are selectable by programming of bit D1. Bit D1 = 0 fast slope (I=Imax) Bit D1 = 1 slow slope (I=Imin) The soft mute generates a gradually decreasing signal, avoiding big click noise of an immediate high attenuation, without necessity to program a sequence of decreasing volume levels. A response example is reported in Figure 11 (mute), and Figure 12 (unmute). The final attenuation obtained with soft mute ON is 60dB typical. The used reference parameter is the delay time taken to reach 20dB attenuation (no matter what the signal level is). Using a capacitor Csm = 22nF this delay is: d = 1. 8mswhen selected Fast slope mode (bit D1=0) d = 25 ms when selected Slow slope mode (bit D1=1 In the application, the soft mute ON programming should be followed by programming of direct mute on (see 5.2), in order to achieve a final 100dB attenuation. In addition to the I2C bus programming, the Soft Mute ON can be generated in a fast way by forcing a LOW level at pin SMEXT (TTL Level compatible). This approach is recommended for fast RDS AF switching. The Soft Mute status can be detected via I2C bus, reading the Transmitted Byte, bit SM (see Table 6). read bit SM = 1 soft mute status ON read bit SM = 0 soft mute status OFF
5.2
Direct mute
bit D3 = 1 Direct mute ON bit D3 = 0 Direct mute OFF The direct mute bit forces an internal immediate signal connection to ground. It is located just before the Volume/Loudness stage, and gives a typical 100dB attenuation.
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TDA7437N
Mute and pause features
5.3
Speakers mute
An additional direct mute function is included in the speakers attenuators stage. The four output LF, RF, LR, RR can be separately muted by setting the speaker attenuator byte to the value 01111111 binary. Typical attenuation level 100dB. This mute is useful for fader and balance functions. It should not be applied for system mute/unmute, because it can generate noise due to the offset of previous stages (bass / treble).
5.4
Zero crossing mute
bit D2 = 1 D4 = 0 zero crossing mute ON bit D2 = 0 D4 = 0 zero crossing mute OFF The mute activation/deactivation is delayed until the signal waveform crosses the DC zero level (Vref level). The detection works separately for left and right channels (see Figure 13 and Figure 14). Four different window thresholds are software selectable by two dedicated bits. bit D6 bit D5 Window 0 0 1 1 0 1 0 1 Vref DC +/-280mV Vref DC +/-140mV Vref DC +/-70mV Vref DC +/-35mV
The zero crossing mute activation/deactivation starts when the AC signal level falls inside the selected window (internal comparator). The zero crossing mute (and pause) detector is always active. It can be disabled, if the feature is not used, by forcing the bit D4 = 1 Zero crossing and pause detector reset. In this way the internal comparator logic is stopped, eliminating its switching noise. The zero cross mute status is detected reading the transmitted byte bit ZM. bit ZM = 1 zero cross mute status ON bit ZM = 0 zero cross mute status OFF
5.5
Pause function
On chip is implemented by a pause detector block. It uses the same 4 windows threshold selectable for the zero crossing mute, bit D6,D5 byte MUTE (see above). The detector can be put into OFF by forcing bit D4 = 1, otherwise it is active. Pause detector information is available at the PAUSE pin. A capacitor must be connected between the PAUSE pin and ground.
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Mute and pause features
TDA7437N
When the incoming signal is detected to be outside the selected window, the external capacitor is discharged. When the signal is inside the window, the capacitor is integrating up (see Figure 15 and Figure 16). a) b) by reading directly the Pause pin level.The ON/OFF voltage threshold is 3.0V typical. Pause OFF = level low (< 3.0V) Pause ON = level high ( ; 3.0V) by reading via I2C bus the transmitted byte, bit PP = 0 pause active. P = 1 no pause detected. The external capacitor value fixes the time constant.
The pull up current is 25uV typical, with input signal Vin = 1Vrm --; Vdc pin pause = 15mV Vin = 0Vrms --; Vdc pin pause = 5.62V For example choosing Cpause = 100nF the charge up constant is about 22ms. Instead with Cpause = 15nF the charge up constant is about 360s. The pause detection is useful in applications like RDS, to perform noiseless tuning frequency jumps, avoiding the use of the mute.
5.6
No symmetrical bass cut response
bit D7 = 0 No symmetrical bit D7 = 1 Symmetrical The bass stage has the option to generate an unsymmetrical response, for cut mode settings (bass level from -2db to - 14dB) For example using a T-type band pass external The feature is useful for human ear equalization in a noisy environment, like a car. See examples in Figure 17 (symmetrical response) and Figure 18 (unsymmetrical response).
5.7
Transmitted data (send mode)
bitP = 0Pause active bitP = 1No pause detected bitZM = 1Zero cross mute ON bitZM = 0Zero cross mute OFF bitSM = 1Soft mute ON bitSM = 0Soft mute OFF bitST = 1Stereo signal detected (input MPX) bitST = 0Mono signal detected (input MPX) The TDA7437N allows the reading of four info bits.
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TDA7437N
Mute and pause features The type (stereo/mono) of received broadcasting signal is easily checked and displayed by using the ST bit. The P bit check is useful in tuning jumps without signal muting. The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON, MUTE byte) and not when the signal level has reached the 60 dB final attenuation.
5.8
TDA7437N I2C bus protocol
The protocol is standard I2C, using subaddress byte plus data bytes (as shown within Chapter 4). The optional autoincrement mode allows to refresh all the bytes registers with transmission of a single subaddress, reducing drastically the total transmission time. Without autoincrement, subaddress bit I = 0, to refresh all the bytes registers (10), it is necessary to transmit 10 times the chip address, the subaddress and the data byte. Working with a 100Kb/s clock speed the total time would be : [(9*3+2)*10]bits*10us=2.9ms Instead using autoincrement mode, subaddress bit I=1, the total time will be: (9*12+2)*10us=1.1ms. The autoincrement mode is useful also to refresh partially the data. For example to refresh the 4 speakers attenuators it is possible to program the subaddress Spkr LF (code XX010100), followed by the data byte of SPKR LF, LR, RF, RR in sequence. Note: that the autoincrement mode has a module 16 counter, whereas the total used register bytes are 10. It is not correct to refresh all the 10 bytes starting from a subaddress different than XX010000. For example; using subaddress XX010010 (volume), the registers from Volume to Mute (see Table 5) are correctly updated, but the next two transmitted bytes, refer instead to the wanted Input selector, and Loudness are discharged. (the solution in this case is to send two separate patterns in autoincrement mode, the first composed by address, subaddress XX010010, 8 data bytes, and the second composed by address, subaddress XX010000, 2 data bytes). With autoincrement disabled, the protocol allows the transmission in sequence of N data bytes of a specific register, without the necessity to resend the address and subaddress bytes, each time. This feature can be implemented, for example, if a gradual volume change has to be performed (the MCU does not send the STOP condition, but keeps the TDA7437N communication active).
Warning:
The TDA7437N always needs to receive a STOP condition, before beginning a new START condition. The device doesn't recognize a START condition if a previously active communication was not ended by a STOP condition.
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Mute and pause features
TDA7437N
5.9
I2C bus read mode
The TDA7437N sends the master a 1 byte "transmitted info" via I2C bus in read mode. The read mode is master activated by sending the chip address with LSB set to 1, followed by an acknowledge bit. The TDA7437N recognizes the request. At the following master generated clock bits, the TDA7437N issues the transmitted inFO byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can:

acknowledge the reception, starting in this way the transmission of another byte from the TDA7437N. no acknowledge, stopping the read mode communication.
5.10
Loudness stage
The previous SGS-THOMSON audioprocessors implemented a fixed loudness response, only ON/OFF sw programmable. No possibility to change the loud boost rate at a certain volume level. The TDA7437N implements a fully programmable loudness control in 20 steps of 1dB. It allows a customized loudness response for each application. The external network connected to the loudness pins LOUD_L and LOUD_R fixes the type of loudness response. 1. 2. 3. 4. Simple capacitor. The loudness effect is only a boost of low frequencies. (see Figure 19) Second order loudness (boost of low and high frequencies). Second order decreased type loudness (lower boost of low and high frequencies). Second order modified type loudness (higher boost of low and high frequencies).
5.11
Treble stage
The treble stage is a simple high pass filter, it's time constant is fixed by internal resistor (typically 50Kohm), and an external capacitor, connected between pins TREB_R/TREB_L and ground.
5.12
IN-OUT pins
The multiplexer output is available at OUT_R and OUT_L pins for the optional connection of an external graphic equalizer (TDA7316/TDA7317), surround chip (TDA7346) etc. The signal is fed in again at pins IN_L and IN-R. In the case of an application without any external devices, the pins OUT_L/OUT_R and IN_L/IN_R can be left unconnected, if bit D3 byte input selector is forced = 0 (DC connect). Instead if bit D3 is kept = 1 an external decoupling capacitor must be provided between OUTR/INR and OUTL/INR to avoid signal DC jumps, generating "clicking" output noise. The input impedance of the next volume stage is 44Kohm typical (minimum 31Kohm). A capacitor no lower than 1mF should be used.
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TDA7437N
Mute and pause features
5.13
Bass & mid filters
Several bass filter types can be implemented. Normally it is the basic T-type bandpass filter that is used. Starting from the filter component values (R1 internal and R2, C1, C2 external), the centre frequency Fc, the gain Av at max bass boost and the filter Q factor are computed as follows: 1 F c = ----------------------------------------------------------------2 R1 R2 C1 C2 R2 C2 + R2 C1 + R1 C1 A v = ------------------------------------------------------------------------R2 C1 + R2 C2 Vice versa fixed Fc, Av, and R1 (internal typ.30%), the external component values are Av - 1 C1 = --------------------------------2 R1 Q Q Q C1 C2 = ----------------------------------Av - 1 - Q Q ( R1 R2 C1 C2 ) Q = ----------------------------------------------------R2 C1 + R2 C2 Av - 1 - Q Q R2 = --------------------------------------------------------------------2 C1 F c ( A v - 1 ) Q
5.14
Input selector
The multiplexer selector can choose one of the following inputs:

a differential CD stereo input. a mono input. four stereo input
The signal fed to the input pins must be decoupled via series capacitors. The minimum allowed value depends on the correspondent input impedance. For the CD diff input (Zi = 10Kohm worst case) a Cin = 4.7uF is recommended. For the other inputs (70Kohm worst case, a Cin=1uF is recommended.
27/34
Curves of electrical characteristics
TDA7437N
6
Figure 7.
Curves of electrical characteristics
Power on time constant vs CREF capacitor CREF = 4.7F
D95AU380
Figure 8.
Power on time constant vs CREF capacitor CREF = 10F
D95AU381
V (1V/div)
V (1V/div)
OUT LF CREF
2 1
OUT LF CREF
2 1
BWL
0.5s/DIV TIME
BWL
0.5s/DIV
TIME
Figure 9.
Power on time constant vs CREF capacitor CREF = 22F
D95AU382
Figure 10. SVRR vs. frequency
V (1V)
SVRR (dB) -40 -50
F 22
D95AU383
4.7F
-60
F 10
47F
-70 OUT LF CREF 2 1 -80 -90 -100 BWL 1s/DIV TIME 10 100 1K 10K Freq(Hz)
VS=8V Ripple=0.2VRMS AV=-15dB
Figure 11. Soft mute ON (a)
V
(b)
SOFT MUTE=ON SLOPE=FAST Vout=500mVrms V
D95AU384
Main Menu
Vout Chan 2 1ms 0.2V Chan 3 1ms 2V
Pin Csm
CH1 9V DC SOFT MUTE
x TIME CH1 0.5V 10 ~ x CH2 20mV10 ~ x CH3 0.2V10 = x CH4 20mV 10 = T/div 1ms
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TDA7437N
Curves of electrical characteristics
Figure 12. Soft mute OFF (a)
V V
(b)
Main Menu Vout Chan 2 1ms 0.2V SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms
D95AU387
Chan 1 1ms 2V
Pin Csm CH1 9V DC SOFT MUTE TIME
Figure 13. Zero crossing mute ON
ZERO CROSSING MUTE = ON V Panel STATUS Memory Save PANEL Recall Auxiliary Setups Memory Card X-Y mode Persistance mode Return RIGHT CH2 528mV DC TIME LEFT
D95AU389
Figure 14. Zero crossing mute OFF
ZERO CROSSING MUTE = OFF x Chan 1 0.5ms 0.2V x Chan 2 0.5ms 0.2V Multi Zoom off V Main Menu LEFT
D95AU390
RIGHT
x Chan 2 0.2ms 1V x Chan 1 0.2ms 0.5V
2ms
CH1 2.7V DC
TIME
Figure 15. Pause detector
PAUSE DETECTOR ZCW=140mV Cpause=100nF D02AU1385 V Vout Main Menu
Figure 16. Pause detector
US CO C Vout Main Menu 0 Cpause 00
D02AU1386
Chan 1 20ms 0.2V Chan 2 20ms 2V CH2 4.12V DC TIME
Chan 2 20ms 2V Chan 3 20ms 0.2V CH2 4.08V DC
x CH1 20mV10 ~ x BWL CH2 0.2V 10x= CH3 20mV 10 ~ x CH4 5mV 10 ~ T/div 20ms
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Curves of electrical characteristics
TDA7437N
Figure 17. Symmetrical bass
Figure 18. unsymmetrical bass
(dB) 10 5
D95AU393
ATT (dB) 10 5 0
D95AU394
0 -5 -10
-5 -10 -15 -20
-15 10 100 1K 10K Freq(Hz)
-25 10 100 1K 10K Freq(Hz)
Figure 19. Loudness
ATT (dB) 18 16 14 12 10 8 6 4 2 0 10 100 1K 10K
D98AU887
Freq(Hz)
30/34
TDA7437N Figure 20. Test board diagram
GND VCC CON1
Curves of electrical characteristics
C17 22F
C18 100nF JP2 JP1 C19 5.6nF TRL
R4 2.7K
R3 5.6K
C11 18nF
C10 22nF
C8 100nF
C7 100nF
C16 22F
AGND
DVDD
ADDR
AVDD
MIDRI 31
MIDRO 30
BASSRO 27
BASSRI 26 39
CREF 25 BASSLO
C20 5.6nF
C6 100nF
TRR IN_R
44 1 2
43
42
41
40
C21 2.2F C22 4.7nF CON4 C23 4.7F DIFG_R C24 4.7F DIFF_R C25 470nF ST4_R C26 470nF ST1_R C27 470nF ST2_R C28 470nF ST3_R C29 470nF MONO C30 4.7nF LOUDR DIFG_R O_R
24
BASSLI
C5 100nF
3
23
MIDLO
C4 22nF
R2 5.6K
LOUDR
4
22 20
MIDLI I_L
C3 18nF
5 21 6 38 28 37 36 9 O_L SCL SMEX SDA DGND
C2 2.2F
R1 2.7K
CON2 SCL JP3 SMEX SDA DGND R5 50 C14 CON3 LF C13 RF C12 LR C9 RR GND
DIFF_R
ST4_R
7
ST1_R
8
ST2_R
ST3_R
10 34 11 33 12 13 DIFF_R 14 ST4_R 15 ST1_R 16 ST2_R 17 ST3_R 18 CSM 19 PAUSE 35 29 OUTLF
MONO
RF
CON5
32
LR
DIFG_R DIFG_L C31 4.7F DIFF_L C32 4.7F ST4_L C33 470nF ST1_L C34 470nF ST2_L C35 470nF ST3_L C36 470nF
OUTRR
C1 2.2nF
C15 10F
D98AU882
31/34
Package information
TDA7437N
7
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. LQFP44 (10x10) Mechanical data and package dimensions
DIM. A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 K ccc 0.45 11.80 9.80 2.00 8.00 0.80 0.60 1.00 0.75 0.0177 0.0394 3.5(min.),7(max.) 0.10 0.0039 0.05 1.35 0.30 0.09 11.80 9.80 2.00 8.00 12.00 10.00 12.00 10.00 1.40 0.37 mm MIN. TYP. MAX. 1.60 0.15 0.0020 MIN. inch TYP. MAX. 0.0630 0.0059
OUTLINE AND MECHANICAL DATA
1.45 0.0531 0.0551 0.0571 0.45 0.0118 0.0146 0.0177 0.20 0.0035 0.0079
12.20 0.4646 0.4724 0.4803 10.20 0.3858 0.3937 0.4016 0.0787 0.3150 12.20 0.4646 0.4724 0.4803 10.20 0.3858 0.3937 0.4016 0.0787 0.3150 0.0315 0.0295
Note: 1. The size of exposed pad is variable depending of leadframe design pad size. End user should verify "D2" and "E2" dimensions for each device application.
LQFP44 (10 x 10 x 1.40mm) Exposed Pad Down
7278839 C
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TDA7437N
Revision history
8
Revision history
Table 14.
Date 24-Jan-06 01-Dec-06
Document revision history
Revision 1 2 Initial release. Package changed, layout change, text modifications. Changes
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TDA7437N
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